The MC10H161 provides parallel decoding of a three bit binary word to one of eight lines. The MC10H161 is useful in high–speed multiplexer/demultiplexer applications.
The MC10H161 is designed to decode a three bit input word to one of eight output lines. The MC10H161 output will be low when selected while all other output are high. The enable inputs, when either or both are high, force all outputs high.
The MC10H161 is a true parallel decoder. This eliminates unequal parallel path delay times found in other decoder designs. These devices are ideally suited for multiplexer/demultiplexer applications.

• Propagation Delay, 1.0 ns Typical
• Power Dissipation, 315 mW Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible