FEATURES
• Power supply voltage of 1.65 V to 1.95 V
• High performance
   70 ns maximum access time (Flash)
   70 ns maximum access time (SRAM)
• Operating Temperature
   –30 °C to +85 °C
• Package 73-ball FBGA

• FLASH MEMORY
   • 0.17 µm process technology
   • Simultaneous Read/Write operation (Dual Bank)
   • FlexBankTM *1
      Bank A: 16M bit (16KB × 4 and 64KB × 31)
      Bank B: 16M bit (64KB × 32)
      Bank C: 16M bit (64KB × 32)
      Bank D: 16M bit (16KB × 4 and 64KB × 31)
   • Minimum 100,000 program/erase cycles
   • Sector Erase Architecture
      Four 8K words, a hundred twenty-eight 32K words sectors.
      Any combination of sectors can be concurrently erased. Also supports full chip erase.
   • WP Input Pin
      At VIL, allows protection of all sectors, regardless of sector protection/unprotection status
      At VIH, allows removal of sector protection
   • Embedded EraseTM *2 Algorithms
      Automatically preprograms and erases the chip or any sector
   • Embedded ProgramTM *2 Algorithms
      Automatically writes and verifies data at specified address
   • Data Polling and Toggle Bit feature for detection of program or erase cycle completion
   • Automatic sleep mode
      When address remain stable, the device automatically switches itself to low power mode
   • Low VCC write inhibit
   • Erase Suspend/Resume
      Suspends the erase operation to allow a read data and/or program in another sector within the same device resumes the erase operation
   • Sector Protection
      Software command sector locking
   • Please Refer to “MBM29BS64LF” Datasheet in Detailed Function

• SRAM
   • Power Dissipation
      Operating : 50 mA Max
      Standby :15 µA Max
   • Power Down Features using CE1s and CE2s
   • Data Retention Supply Voltage: 1.0 V to 1.95 V
   • CE1s and CE2s Chip Select
   • Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)