datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать
HOME  >>>  Lattice Semiconductor  >>> ISPLSI2128VL PDF

ISPLSI2128VL Даташит - Lattice Semiconductor

ISPLSI2128VL image

Номер в каталоге
ISPLSI2128VL

Other PDF
  no available.

PDF
DOWNLOAD     

page
17 Pages

File Size
196.9 kB

производитель
Lattice
Lattice Semiconductor Lattice

Description
The ispLSI 2128VL is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions.


FEATUREs
• SuperFAST HIGH DENSITY IN-SYSTEM
   PROGRAMMABLE LOGIC
   — 6000 PLD Gates
   — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
   — 128 Registers
   — High Speed Global Interconnect
   — Wide Input Gating for Fast Counters, State
      Machines, Address Decoders, etc.
   — Small Logic Block Size for Random Logic
   — 100% Functional, JEDEC and Pinout Compatible
      with ispLSI 2128V and 2128VE Devices
• 2.5V LOW VOLTAGE 2128 ARCHITECTURE
   — Interfaces with Standard 3.3V Devices (Inputs and
      I/Os are 3.3V Tolerant)
   — 125 mA Typical Active Current
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   — fmax = 150 MHz Maximum Operating Frequency
   — tpd = 6.0 ns Propagation Delay
   — Electrically Erasable and Reprogrammable
   — Non-Volatile
   — 100% Tested at Time of Manufacture
   — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
   — 2.5V In-System Programmability (ISP™) Using
      Boundary Scan Test Access Port (TAP)
   — Open-Drain Output Option for Flexible Bus Interface
      Capability, Allowing Easy Implementation of Wired
      OR Bus Arbitration Logic
   — Increased Manufacturing Yields, Reduced Time-to
      Market and Improved Product Quality
   — Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
   PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
   — Enhanced Pin Locking Capability
   — Three Dedicated Clock Input Pins
   — Synchronous and Asynchronous Clocks
   — Programmable Output Slew Rate Control
   — Flexible Pin Placement
   — Optimized Global Routing Pool Provides Global
      Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
   PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
   SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
   — Superior Quality of Results
   — Tightly Integrated with Leading CAE Vendor Tools
   — Productivity Enhancing Timing Analyzer, Explore
      Tools, Timing Simulator and ispANALYZER™
   — PC and UNIX Platforms

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

Номер в каталоге
Компоненты Описание
PDF
производитель
2.5V In-System Programmable SuperFAST™ High Density PLD
Lattice Semiconductor
In-System Programmable High Density PLD ( Rev : 2002 )
Lattice Semiconductor
In-System Programmable High Density PLD
Lattice Semiconductor
2.5V In-System Programmable SuperFAST™ High Density PLD
Lattice Semiconductor
In-System Programmable High Density PLD ( Rev : 2002 )
Lattice Semiconductor
In-System Programmable High Density PLD
Lattice Semiconductor
In-System Programmable High Density PLD
Lattice Semiconductor
In-System Programmable High Density PLD
Lattice Semiconductor
In-System Programmable High Density PLD
Lattice Semiconductor
In-System Programmable High Density PLD
Lattice Semiconductor

Share Link: GO URL

EnglishEnglish Korean한국어 Chinese简体中文 Russianрусский Spanishespañol

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]