DESCRIPTION
The ISSI IS61SPS25632, IS61SPS25636, IS61SPS51218, IS61LPS25632, IS61LPS25636, and IS61LPS51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance memory for communication and networking applications. The IS61SPS25632 and IS61LPS25632 are organized as 262,144 words by 32 bits and the IS61SPS25636 and IS61LPS25636 are organized as 262,144 words by 36 bits.

FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Linear burst sequence control using MODE input
• Three chip enable option for simple depth expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and 119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 3.3V I/O For SPS
• 2.5V I/O For LPS
• Single cycle deselect
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)