Description
   IN16C554A is an enhanced quadruple version of the 16C550UART (Universal Asynchronous Receiver Transmitter). IN16C554A is in part an upgrade version of IN16C554, as it is designed for 3.3V only and has AUTO-CTS, AUTO-RTS functions.
   In IN16C554A, Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead. In this mode, internal FIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes.

FEATUREs
◾ In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the number of interrupts to CPU.
◾ Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
◾ Holding Register and Shift Register eliminate need for precise synchronization between the CPU and serial data.
◾ Independently controlled transmit, receive, line status and data interrupts.
◾ Programmable Baud Rate Generators which allow division of any input reference clock by 1 to 216-1 and generate an internal 16X clock.
◾ Independent receiver clock input Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#).
◾ Fully programmable serial interface characteristics.
   - 5-, 6-, 7-, or 8-bit characters
   - Even-, Odd-, or No-Parity bit
   1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, IN16C554 checks only one stop bit, no matter how many they are)
◾ False start bit detection
◾ Generates or Detects Line Break
◾ Internal diagnostic capabilities : Loopback controls for communications link fault isolation.
◾ Full prioritized interrupt system controls
◾ Hardware (RTS#/CTS#) Flow Control