DESCRIPTION:
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/72T36125 are exceptionally deep, extrememly high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• A user selectable MARK location for retransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translation on the read or write ports
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 9 Mbit
Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.

FEATURES:
• Choose among the following memory organizations:
   IDT72T3645 ⎯ 1,024 x 36
   IDT72T3655 ⎯ 2,048 x 36
   IDT72T3665 ⎯ 4,096 x 36
   IDT72T3675 ⎯ 8,192 x 36
   IDT72T3685 ⎯ 16,384 x 36
   IDT72T3695 ⎯ 32,768 x 36
   IDT72T36105 ⎯ 65,536 x 36
   IDT72T36115 ⎯ 131,072 x 36
   IDT72T36125 ⎯ 262,144 x 36
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write operations
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost Empty and Almost-Full flags

• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
   - x36 in to x36 out
   - x36 in to x18 out
   - x36 in to x9 out
   - x18 in to x36 out
   - x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm) Plastic Ball Grid Array (PBGA)
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts are available, see ordering information