DESCRIPTION
The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC unit. The chip provides single-error correction and two and three bit error detection of both hard and soft memory errors. It can be expanded to 64-bit widths by cascading 2 units, without the need for additional external logic. The Flow thruEDC has been optimized for speed and simplicity of control.

FEATURES
• 32-bit wide Flow-thruEDC unit, cascadable to 64 bits
• Single-chip 64-bit Generate Mode
• Separate system and memory buses
• On-chip pipeline latch with external control
• Supports bidirectional and common I/O memories
• Corrects all single-bit errors
• Detects all double-bit errors, some multiple-bit errors
• Error Detection Time — 12ns
• Error Correction Time — 14ns
• On chip diagnostic registers.
• Parity generation and checking on system data bus
• Low power CMOS — 100mA typical at 20MHZ
• 144-pin PGA and PQFP packages
• Military product compliant to MIL-STD 883, Class B