The HYM 322035S/GS-50/-60/-70 is a 8 MByte DRAM module organized as 2 097 152 words by 32-bit in a 72-pin single-in-line package comprising four HYB 5117805BSJ 2M × 8 EDO-DRAMs in 400 mil wide SOJ-packages mounted together with four 0.2 µF ceramic decoupling capacitors on a PC board.

Advanced Information
• 2 097 152 words by 32-bit organization
• 1 memory bank
• Fast access and cycle time
    50 ns access time
    84 ns cycle time (-50 version)
    60 ns access time
    104 ns cycle time (-60 version)
    70 ns access time
    124 ns cycle time (-70 version)
• Hyper page mode - EDO capability
    35 ns cycle time (-50 version)
    40 ns cycle time (-60 version)
    45 ns cycle time (-70 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
    max. 2640 mW active (-50 version)
    max. 2420 mW active (-60 version)
    max. 2200 mW active (-70 version)
    CMOS – 22 mW standby
TTL –44 mW standby
• CAS-before-RAS refresh RAS-only-refresh Hidden-refresh
• 4 decoupling capacitors mounted on substrate
• All inputs, outputs and clocks fully TTL compatible
• 72 pin Single in-Line Memory Module (L-SIM-72-9 ) with 20.32 mm (800 mil) height
• Utilizes four 2M × 8 -DRAMs in 400 mil SOJ packages
• 2048 refresh cycles / 32 ms with 11/10 addressing
• Optimized for use in byte-write non-parity applications
• Tin-Lead contact pads (S-version)
• Gold contact pads (GS - version)