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HN29V102414 Даташит - Renesas Electronics

HN29V102414 image

Номер в каталоге
HN29V102414

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48 Pages

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Renesas
Renesas Electronics Renesas

Description
   The Hitachi HN29V102414 Series is a CMOS Flash Memory with AND type multi-level memory cells. It has fully automatic programming and erase capabilities with a single 3.0 V power supply. The functions are controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase is as small as (2048 + 64) bytes. Initial available sectors of HN29V102414 are more than 64,226 (98% of all sector address) and less than 65,536 sectors.


FEATUREs
• On-board single power supply (VCC): VCC = 2.7 V to 3.6 V
• Organization
   – AND Flash Memory: (2048 + 64) bytes × (More than 32,113 sectors) × 2
   – Data register: (2048 + 64) bytes × 2
• Multi-level memory cell
   – 2 bit/per memory cell
• Automatic programming
   – Sector program time: 1.0 ms (typ)
   – System bus free
   – Address, data latch function
   – Internal automatic program verify function
   – Status data polling function
• Automatic erase
   – Single sector erase time: 1.0 ms (typ)
   – System bus free
   – Internal automatic erase verify function
   – Status data polling function
• Erase mode
   – Single sector erase ((2048 + 64) byte unit)
• Fast serial read access time:
   – First access time: 50 µs (max)
   – Serial access time: 50 ns (max)
• Low power dissipation:
   – ICC1 = 2 mA (typ) (Read) (1-chip operation)
      ICC1 = 4 mA (typ) (Read) (2-chip operation)
   – ICC2 = 20 mA (max) (Read) (1-chip operation)
      ICC2 = 40 mA (max) (Read) (2-chip operation)
   – ISB2 = 50 µA (max) (Standby) (1-chip operation)
      ISB2 = 100 µA (max) (Standby) (2-chip operation)
   – ICC3/ICC4 = 40 mA (max) (Erase/Program) (1-chip operation)
      ICC3/ICC4 = 80 mA (max) (Erase/Program) (2-chip operation)
   – ISB3 = 20 µA (max) (Deep standby) (1-chip operation)
      ISB3 = 40 µA (max) (Deep standby) (2-chip operation)
• The following architecture is required for data reliability.
   – Error correction: more than 3-bit error correction per each sector read
   – Spare sectors: 1.8% (579 sectors)/chip (min) within usable sectors


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