General description
The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action.

FEATUREs and benefits
■ Tolerant of slow clock rise and fall time
■ Fully static operation
■ 5 V, 10 V, and 15 V parametric ratings
■ Standardized symmetrical output characteristics
■ Specified from -40 °C to +85 °C
■ Complies with JEDEC standard JESD 13-B

APPLICATIONs
■ Frequency dividing circuits
■ Time delay circuits
■ Control counters