GENERAL DESCRIPTION
The device is a 128Mx8bit with spare 4Mx8bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.

FEATURES
• Voltage Supply: 3.3V (2.7V~3.6V)
• Organization
   - Memory Cell Array: (128M + 4M) x 8bit
   - Data Register: (2K + 64) x 8bit
• Automatic Program and Erase
   - Page Program: (2K + 64) Byte
   - Block Erase: (128K + 4K) Byte
• Page Read Operation
   - Page Size: (2K + 64) Byte
   - Random Read: 25us (Max.)
   - Serial Access: 25ns (Min.) (3.3V)
• Memory Cell: 1bit/Memory Cell
• Fast Write Cycle Time
   - Program time: 400us - typical
   - Block Erase time: 4ms - typical
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
   - Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating Gate Technology
   - ECC Requirement: - 1bit/528Byte
   - Endurance: 100K Program/Erase cycles
   - Data Retention: 10 years
• Command Register Operation
• Automatic Page 0 Read at Power-Up Option
   - Boot from NAND support
   - Automatic Memory Download
• NOP: 4 cycles
• Cache Program Operation for High Performance Program
• Cache Read Operation
• Copy-Back Operation
• EDO mode
• OTP Operation
• Bad-Block-Protect