Functional Description
The CY7C1460AV33/CY7C1462AV33 are 3.3 V, 1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460AV33/CY7C1462AV33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1460AV33/CY7C1462AV33 are pin compatible and functionally equivalent to ZBT devices.

FEATUREs
■ Pin compatible and functionally equivalent to ZBT
■ Supports 250 MHz bus operations with zero wait states
   ❐ Available speed grades are 250, 200 and 167 MHz
■ Internally self timed output buffer control to eliminate the need to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ 3.3 V power supply
■ 3.3 V/2.5 V I/O power supply
■ Fast clock-to-output times
   ❐ 2.6 ns (for 250 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self timed writes
■ CY7C1460AV33, CY7C1462AV33 available in
   JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
   Pb-free 165-ball FBGA package.
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability—linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option