Functional Description
The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems.

FEATUREs
• 500-ps max. Total Timing Budget™ (TTB™) window
• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V) input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
• 18 LVTTL outputs driving 50Ω terminated lines
• 16 outputs at 200 MHz: Commercial temperature
• 6 outputs at 200 MHz: Industrial temperature
• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable reference inputs
• Phase adjustments in 625-/1300-ps steps up to ± 10.4 ns
• Multiply/divide ratios of 1–6, 8, 10, 12
• Individual output bank disable
• Output high-impedance option for testing purposes
• Fully integrated phase-locked loop (PLL) with lock indicator
• <50-ps typical cycle-to-cycle jitter
• Single 3.3V ± 10% supply
• 100-pin TQFP package
• 100-lead BGA package