ACT5260 DESCRIPTION:
The ACT5260 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 64-bit system interface. The ACT5260 can issue both an integer and a floating point instruction in the same cycle.

The Aeroflex ACT5260PC-P10-POD adapts a QED RM5260 MIPS microprocessor to an R4400PC, R4600 or R4700 processor’s 179 pin PGA footprint. This product allows the evaluation of the latest MIPS IV 5XXX series performance in existing 4XXX series hardware. Some of the performance enhancements include:

■ Allows potentially higher pipeline clock rates due to it multiplication of the input clock by 2,3,4,5,6,7 or 8 compared to the 4XXX series method of multiplying the input clock by only 2, then dividing it down by 2,3,4 etc for output system clock.
■ The RM5260 is a 3.3 volt device with 5 volt tolerant I/O’s.
■ It has a fully operational IEEE 1149.1 JTAG boundary scan interface.
■ On-board supply de-coupling capacitors and PLL filter network.