DESCRIPTION
The ACT5231 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 32KB 2-way set associative instruction cache, a 32KB 2-way set associative data cache, and an efficient 32-bit system interface. The ACT5231 can issue both an integer and a floating point instruction in the same cycle.

FEATUREs
■ Full militarized QED RM5231 microprocessor
■ Pinout compatible with popular RM5230 with split power sup plies (2.5V and 3.3V)
■ Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle
    ● 133, 150 and 200 MHz operating frequencies – Consult Factory for latest speeds
    ● 325 Dhrystone2.1 MIPS
    ● SPECInt95 5.0, SPECfp95 5.25
■ System interface optimized for embedded applications
    ● 32-bit system interface lowers total system cost
    ● High performance write protocols maximize uncached write bandwidth with 600 MB per second peak throughput
    ● Operates at processor clock divisors 2, 2.5, 3, 3.5,4, 4.5, 5, 6, 7, 8, 9
    ● IEEE 1149.1 JTAG boundary scan
■ Integrated on-chip caches
    ● 32KB instruction and 32KB data - 2 way set associative and per set locking
    ● Virtually indexed, physically tagged
    ● Write-back and write-through on per page basis
    ● Pipeline restart on first double for data cache misses
■ Integrated memory management unit
    ● Fully associative joint TLB (shared by I and D translations)
    ● 48 dual entries map 96 pages
    ● Variable page size (4KB to 16MB in 4x increments)
■ High-performance floating point unit
    ● 532 MFLOPS single-precision performance
    ● Single cycle repeat rate for common single precision opera-tions and some double precision operations
    ● Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations
    ● Single cycle repeat rate for single precision combined multiplyadd operation
■ MIPS IV instruction set
    ● Floating point multiply-add instruction increases performance in signal processing and graphics applications
    ● Conditional moves to reduce branch frequency
    ● Index address modes (register + register)
■ Embedded application enhancements
    ● Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction
    ● I and D cache locking by set
    ● Optional dedicated exception vector for interrupts
■ Fully static CMOS design with power down logic
    ● Standby reduced power mode with WAIT instruction
    ● 2.7 W typical power @ 200MHz
    ● 2.5V core with 3.3V IO’s
■ 128-pin Power Quad-4 package (F22), Consult Factory for package configuration