DESCRIPTION
The 74F597 consists of an 8-bit storage register feeding a parallel-in/serial-in, serial-out 8-bit shift register. The storage register and shift register have separate positive edge triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous load.

FEATURES
• High impedance PNP base inputs for reduced loading (20µA in High and Low states)
• 8-bit parallel storage register
• 3-State output buffers
• Shift register has asynchronous direct overriding reset
• Shift load SHLD is functional when SHCP is Low and locked out when SHCP is High
• Guaranteed shift frequency DC to 105MHz