DESCRIPTION
The 74ALVT16841 Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V.

FEATURES
• High speed parallel latches
• 5V I/O Compatible
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or buses carrying parity
• Power-up 3-State
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model