DESCRIPTION
The ACT161 is a high-speed CMOS SYNCRONOUS PRESETTABLE COUNTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power applications mantaining high speed operation similar to eqivalent Bipolar Schottky TTL. It is a 4 bit binary counter with Asynchronous Clear.
The circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. Four control inputs, Master Reset (CLEAR), Parallel Enable Input (LOAD), Count Enable Input (PE) and Count Enable Carry Input (TE), determine the mode of operation as shown in the Truth Table. A LOW signal on CLEAR overrides counting and parallel loading and sets all outputs on LOW state. A LOW signal on LOAD overrides counting and allows information on Parallel Data Qn inputs to be loaded into the flip-flops on the next rising edge of CLOCK. With LOAD and CLEAR, PE and TE permit counting when both are HIGH. Conversely, a LOW signal on either PE and TE inhibits counting.
The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   fMAX =125 MHz (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC =8 µA (MAX.) at TA = 25 °C
■ COMPATIBLEWITH TTL OUTPUTS
   VIH = 2V (MIN), VIL = 0.8V(MAX)
■ 50Ω TRANSMISSIONLINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24 mA (MIN)
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 161
■ IMPROVED LATCH-UP IMMUNITY