General Description
These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures that all outputs remain off for all invalid (10–15) input conditions.

FEATUREs
■ Diode clamped inputs
■ Also for application as 4-line-to-16-line decoders;
   3-line-to-8-line decoders
■ All outputs are high for invalid input conditions
■ Typical power dissipation 140 mW
■ Typical propagation delay 17 ns