STLC1511 Просмотр технического описания (PDF) - STMicroelectronics
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STLC1511 Datasheet PDF : 31 Pages
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Figure 9. Serial Interface Block Diagram
STLC1511
TXSIN[1:0]
FRMCLK
CK35M
2
QD
S DATA
SOUT
8-bit Shift Register (x2)
CK
O U T[15:0]
14
O u t[ 1 5:0 ]
QD
QD
QD
DQ
(x14)
to DAC parallel input
(Note: DAC input is
sampled on posedge
CKDAC)
14
CKDAC
(4.416MHz Clock from PLL)
QD
QD
QD
(4.416MHz Clock from PLL)
QD
CKADC
(4 Dff to align data
edges as required)
RXSOUT[1:0] 2
2
QD
SOUT
LD
LD
SD ATA
(x2)
8-bit Shift Register (x2)
D ATA [15:0] CK
12
D a ta [ 15 :0 ]
QD
(x12)
from ADC parallel output
(Note: ADC output changes
on posedge of CKADC)
12
CK35M
FRMCLK
TX SIN [0 ]
TX SIN [1 ]
RXSOUT[0]
RXSOUT[1]
CKDAC
CKADC
a5 a4
a3 a2 a1 lsb
msb a12 a11 a10 a9
a8 a7
a6
b3 b2 b1 lsb
msb b10 b9 b8
b7
b6 b5 b4
Data clocked out by
ADC on this edge
Data sampled by
DAC on this edge
3.6.1 ADC Clip Indicator
Normally, the receive signal level is set such that the
input to the STLC1511 plus the RxPGA gain will not
saturate the input to the ADC converter (for maxi-
mum ADC input levels).
If the input signal is too large however and causes the
ADC to clip, the STLC1511 will report to the digital
chip that a clip has occurred. This is accomplished by
forcing the output data stream supplied to the digital
chip to either “7FFF” hex for an out of range positive
input or to “8000” hex for an out of range negative in-
put. This is highlighted in Figure 10.
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