CY7C109B-20VI(2005) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C109B-20VI
(Rev.:2005)

128K x 8 Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle No. 1[10, 11]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

CY7C109B

CY7C1009B

DATA VALID

Read Cycle No. 2 (OE Controlled)[11, 12]

ADDRESS

CE1

CE2

OE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]

ADDRESS

CE1

CE2

WE

DATA I/O

tSA

tAW

tWC

tSCE

tPWE

tSCE

tSD

DATA VALID

tHA

tHD

Notes:

10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

11. WE is HIGH for read cycle.

12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

Document #: 38-05038 Rev. *B

Page 6 of 11

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