IDT79R4640100DU Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT79R4640100DU

LOW-COST EMBEDDED ORION™ RISC MICROPROCESSOR

Integrated Device Technology 

R4640/RV4640

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE

The interface consists of a 64-bit Address/Data bus with

8 check bits and a 9-bit command bus protected with

parity. In addition, there are 8 handshake signals and 6

interrupt inputs. The interface has a simple timing specifi-

cation and is capable of transferring data between the

processor and memory at a peak rate of 533MB/sec at

133MHz.

Figure 4 shows a typical system using the R4640. In

this example two banks of DRAMs are used to supply and

accept data with a DDxxDD data pattern.

The R4640 clocking interface allows the CPU to be

easily mated with external reference clocks. The CPU

input clock is the bus reference clock, and can be

between 25 and 67MHz (somewhat dependent on

maximum pipeline speed for the CPU).

An on-chip phase-locked-loop generates the pipeline

clock from the system interface clock by multiplying it up

an amount selected at system reset. Supported multi-

pliers are values 2 through 8 inclusive, allowing systems

to implement pipeline clocks at significantly higher

frequency than the system interface clock.

System Address/Data Bus

The 64-bit System Address Data (SysAD) bus is used

to transfer addresses and data between the R4640 and

the rest of the system. It is protected with an 8-bit parity

check bus, SysADC. When initialized for 32-bit operation,

SysAD can be viewed as a 32-bit multiplexed bus, with 4

parity check bits.

The system interface is configurable to allow easier

interfacing to memory and I/O systems of varying

frequencies. The bus frequency and reference timing of

the R4640 are taken from the input clock. The rate at

which the CPU transmits data to the system interface is

programmable via boot time mode control bits. The rate at

which the processor receives data is fully controlled by

the external device. Therefore, either a low cost interface

requiring no read or write buffering or a faster, high perfor-

mance interface can be designed to communicate with

the R4640. Again, the system designer has the flexibility

to make these price/performance trade-offs.

System Command Bus

The R4640 interface has a 9-bit System Command

(SysCmd) bus. The command bus indicates whether the

SysAD bus carries an address or data. If the SysAD

carries an address, then the SysCmd bus also indicates

what type of transaction is to take place (for example, a

read or write). If the SysAD carries data, then the SysCmd

bus also gives information about the data (for example,

this is the last data word transmitted, or the cache state of

this data line is clean exclusive). The SysCmd bus is

bidirectional to support both processor requests and

external requests to the R4640. Processor requests are

initiated by the R4640 and responded to by an external

device. External requests are issued by an external

device and require the R4640 to respond.

The R4640 supports single datum (one to eight byte)

and 8-word block transfers on the SysAD bus. In the case

of a single-datum transfer, the low-order 3 address bits

gives the byte address of the transfer, and the SysCmd

bus indicates the number of bytes being transferred. The

choice of 32- or 64-bit wide system interface dictates

whether a cache line block transaction requires 4 double

Boot

ROM

DRAM

(80ns)

Address

Control

SCSI

ENET

RV4640

32

Memory I/O

Controller

9

2

11

Figure 4: Typical R4640 System Architecture

7

Share Link: