IDT79R4640100DU Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT79R4640100DU

LOW-COST EMBEDDED ORION™ RISC MICROPROCESSOR

Integrated Device Technology 

R4640/RV4640

COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE

Opcode

Operand Latency

Size

Repeat

Stall

MULT/U,

16 bit

3

MAD/U

32 bit

4

2

0

3

0

MUL

16 bit

3

2

1

32 bit

4

3

2

D M U L T,

any

6

DMULTU

5

0

DIV, DIVU

any

36

36

0

D D I V,

DDIVU

any

68

68

0

Table 1: R4640 Integer Multiply Operation

The MIPS-III architecture defines that the results of a

multiply or divide operation are placed in the HI and LO

registers. The values can then be transferred to the

general purpose register file using the MFHI/MFLO

instructions.

The R4640 adds a new multiply instruction, “MUL”,

which can specify that the multiply results bypass the “Lo”

register and are placed immediately in the primary

register file. By avoiding the explicit “Move-from-Lo”

instruction required when using “Lo”, throughput of

multiply-intensive operations is increased.

An additional enhancement offered by the R4640 is an

atomic “multiply-add” operation, MAD, used to perform

multiply-accumulate operations. This instruction multiplies

two numbers and adds the product to the current contents

of the HI and LO registers. This operation is used in

numerous DSP algorithms, and allows the R4640 to cost

reduce systems requiring a mix of DSP and control

functions.

Finally, aggressive implementation techniques feature

low latency for these operations along with pipelining to

allow new operations to be issued before a previous one

has fully completed. Table 1 also shows the repeat rate

(peak issue rate), latency, and number of processor stalls

required for the various operations. The R4640 performs

automatic operand size detection to determine the size of

the operand, and implements hardware interlocks to

prevent overrun, allowing this high-performance to be

achieved with simple programming.

The floating-point unit of the R4640 directly imple-

ments single-precision floating-point operations, which

enables the R4640 to perform functions such as graphics

rendering without requiring extensive die area or power

consumption. The single-precision unit of the R4640 is

directly compatible with the single-precision operation of

the R4700, and features the same latencies and repeat

rates.

The R4640 does not directly implement the double-

precision operations found in the R4700. However, to

maintain software compatibility, the R4640 will signal a

trap when a double-precision operation is initiated,

allowing the requested function to be emulated in

software. Alternatively, the system architect could use a

software library emulation of double-precision functions,

selected at compile time, to eliminate the overhead

associated with trap and emulation.

Floating-Point Units

The R4640’s floating-point execution units perform

single precision arithmetic, as specified in IEEE Standard

754. The execution unit is broken into a separate multiply

unit and a combined add/convert/divide/square root unit.

Overlap of multiply and add/subtract is supported. The

multiplier is partially pipelined, allowing a new multiplica-

tion instruction to begin every 6 cycles.

As in the IDT79R4700, the R4640 maintains fully

precise floating-point exceptions while allowing both

overlapped and pipelined operations. Precise exceptions

are extremely important in mission-critical environments,

such as ADA, and highly desirable for debugging in any

environment.

The floating-point unit’s operation set includes floating-

point add, subtract, multiply, divide, square root,

conversion between fixed-point and floating-point format,

conversion among floating-point formats, and floating-

point compare. These operations comply with IEEE

Standard 754. Double precision operations are not

directly supported; attempts to execute double-precision

floating point operations, or refer directly to double-

precision registers, result in the R4640 signalling a “trap”

to the CPU, enabling emulation of the requested function.

Floating-Point Coprocessor

The R4640 incorporates an entire single-precision

floating-point coprocessor on chip, including a floating-

point register file and execution units. The floating-point

coprocessor forms a “seamless” interface with the integer

unit, decoding and executing instructions in parallel with

the integer unit.

3

Share Link: