ADV7403KSTZ-140(RevSpA) Просмотр технического описания (PDF) - Analog Devices
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ADV7403KSTZ-140
(Rev.:RevSpA)
(Rev.:RevSpA)
Analog Devices
ADV7403KSTZ-140 Datasheet PDF : 24 Pages
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ADV7403
TIMING CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 3.
Parameter1, 2, 3
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range4
I2C PORT5
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)6
Data Output Transition Time SDR (SDP)6
Data Output Transition Time SDR (CP)7
Data Output Transition Time SDR (CP)7
Data Output Transition Time DDR (CP)7, 8
Data Output Transition Time DDR (CP)7, 8
Data Output Transition Time DDR (CP)7, 8
Data Output Transition Time DDR (CP)7, 8
DATA and CONTROL INPUTS5
Input Setup Time (Digital Input Port)
Input Hold Time (Digital Input Port)
Symbol Test Conditions
Min
Typ
Max Unit
14.8
12.825
28.63636
MHz
±50 ppm
110 kHz
140 MHz
400 kHz
t1
0.6
μs
t2
1.3
μs
t3
0.6
μs
t4
0.6
μs
t5
100
ns
t6
300 ns
t7
300 ns
t8
0.6
μs
5
ms
t9:t10
45:55
55:45 % duty
cycle
t11
Negative clock edge to start of
valid data
t12
End of valid data to negative
clock edge
t13
End of valid data to negative
clock edge
t14
Negative clock edge to start of
valid data
t15
Positive clock edge to end of −4 + TLLC1/4
valid data
t16
Positive clock edge to start of 0.25 + TLLC1/4
valid data
t17
Negative clock edge to end of −2.95 + TLLC1/4
valid data
t18
Negative clock edge to start of −0.5 + TLLC1/4
valid data
3.6 ns
2.4 ns
2.8 ns
0.1 ns
ns
ns
ns
ns
t19
HS_IN, VS_IN
9
ns
DE_IN, data inputs
2.2
ns
t20
HS_IN, VS_IN
7
ns
DE_IN, data inputs
2
ns
1 The min/max specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
3 Guaranteed by characterization.
4 Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110.
5 TTL input values are 0 V to 3 V, with rise/fall times ≥3 ns, measured between the 10% and 90% points.
6 SDP timing figures obtained using default drive strength value (0xD5) in register subaddress 0xF4.
7 CP timing figures obtained using max drive strength value (0xFF) in Register Subaddress 0xF4.
8 DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
Rev. SpA | Page 7 of 24
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