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W83195BR-25

200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET

Winbond 

W83195BR-25

# - Active Low

* - Internal 250kΩ pull-up

PRELIMINARY

4.1 Crystal I/O

SYMBOL

Xin

Xout

PIN

I/O

FUNCTION

2

IN Crystal input with internal loading capacitors(36pF)

and feedback resistors.

3

OUT Crystal output at 14.318MHz nominally with internal

loading capacitors(36pF).

4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs

SYMBOL

PIN

I/O

FUNCTION

CPUCLK [0:1]

52,51

OUT Low skew (< 250ps) clock outputs for host

frequencies such as CPU and Chipset.

PD#/RESET$

22

IN Mode1*=1, Power Down mode when driven low.

Mode1*=0, RESET# open drain (4ms low active

pulse when Watch Dog time out)

IOAPIC

54

OUT Clock outputs synchronous with PCI clock and

powered by VddA.

SDRAM_F,

SDRAM[0:11]

38, 48,47,46,

44,43,42,40,

39,31, 30,27,

26

OUT SDRAM clock outputs.

PCICLK0/ FS0&

11

I/O 3.3V 33MHz PCI clock during normal operation.

Latched input for FS0 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks(Default=0).

PCICLK1/ *FS1

12

I/O Low skew (< 250ps) PCI clock outputs.

Latched input for FS1 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks(Default=1).

PCICLK2/ *SEL24_48

13

I/O Low skew (< 250ps) PCI clock outputs.

Latched input for SEL24_48 at initial power up for the

output frequency of 24MHz(HIGH) and 48MHz(LOW)

clocks.

PCICLK3/ Mode1*

15

I/O Low skew (< 250ps) PCI clock outputs.

Latched input for Mode* pin at initial power up for the

output PD# /RESET# output selection.

PCICLK [ 4:7 ]

16,17,19,20 OUT Low skew (< 250ps) PCI clock outputs.

3V66 [0:2]

6,7,8

OUT 3.3V output clocks for the chipset.

Publication Release Date: May 2000

-3-

Revision 0.52

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