CY62128EV30 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY62128EV30 Datasheet PDF : 12 Pages
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CY62128EV30 MoBL®
Figure 5. Data Retention Waveform [10]
DATA RETENTION MODE
VCC
VCC(min)
VDR > 1.5V
VCC(min)
tCDR
tR
CE
Switching Characteristics
(Over the Operating Range)[10, 11]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
Write Cycle[14]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[12]
OE HIGH to High Z[12,13]
CE LOW to Low Z[12]
CE HIGH to High Z[12, 13]
CE LOW to Power Up
CE HIGH to Power Down
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z[12, 13]
WE HIGH to Low Z[12]
45 ns (Industrial/Auto-A)
Min
Max
55 ns (Auto-E)
Min
Max
45
55
45
55
10
10
45
55
22
25
5
5
18
20
10
10
18
20
0
0
45
55
45
55
35
40
35
40
0
0
0
0
35
40
25
25
0
0
18
20
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
10. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
11. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
13. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05579 Rev. *E
Page 5 of 12
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