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EVAL-AD7923CB

4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP

Analog Devices 

AD7923

ADD1

0

0

1

1

Table II. Channel Selection

ADD0

0

1

0

1

Analog Input Channel

VIN0

VIN1

VIN2

VIN3

Table III. Power Mode Selection

PM1 PM0 Mode

1 1 Normal Operation. In this mode, the AD7923 remains in full power mode, regardless of the status of any of the logic

inputs. This mode allows the fastest possible throughput rate from the AD7923.

1 0 Full Shutdown. In this mode, the AD7923 is in full shutdown mode with all circuitry on the AD7923 powering down.

The AD7923 retains the information in the Control Register while in full shutdown. The part remains in full shutdown

until these bits are changed.

0 1 Auto Shutdown. In this mode, the AD7923 automatically enters full shutdown mode at the end of each conversion

when the Control Register is updated. Wake-up time from full shutdown is 1 ms, and the user should ensure that 1 ms has

elapsed before attempting to perform a valid conversion on the part in this mode.

0 0 Invalid Selection. This configuration is not allowed.

SEQUENCER OPERATION

The configuration of the SEQ1 and SEQ0 bits in the Control

Register allows the user to select a particular mode of operation

of the sequencer function. Table IV outlines the three modes of

operation of the sequencer.

Table IV. Sequence Selection

SEQ1 SEQ0 Sequence Type

0

X

This configuration means that the sequence function is not used. The analog input channel selected for each

individual conversion is determined by the contents of the channel address bits ADD1, ADD0 in each prior write

operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer

function being used, where each write to the AD7923 selects the next channel for conversion. (See Figure 2.)

1

0

If the SEQ1 and SEQ0 bits are set in this way, the sequence function will not be interrupted upon completion of the

WRITE operation. This allows other bits in the Control Register to be altered between conversions while in a

sequence without terminating the cycle.

1

1

This configuration is used in conjunction with the channel address bits ADD1, ADD0 to program continuous

conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the

channel address bits in the Control Register. (See Figure 3.)

–10–

REV. 0

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