ISL97673 Просмотр технического описания (PDF) - Renesas Electronics
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ISL97673 Datasheet PDF : 28 Pages
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ISL97673
Electrical Specifications
All specifications below are tested at TA = +25°C; VIN = 12V, EN/PWM = 5V, RSET = 20.1k, unless otherwise noted.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8) UNIT
Guaranteed Range for PWMI Input Low
VIL
Voltage
0.8
V
Guaranteed Range for PWMI Input High
VIH
Voltage
1.5
VDD
V
PWMI Input Frequency Range
FPWM
200
30,000 Hz
PWM Input Accuracy
PWMACC
8
bits
PWM Dimming Frequency Range
FPWM
RFPWM = 660k
90
100
110
Hz
Direct PWM Minimum On Time
tDIRECTPWM Direct PWM Mode
250
350
ns
FAULT PIN
Fault Pull-down Current
IFAULT
VIN = 12V
12
21
30
µA
Fault Clamp Voltage with Respect to VIN
VFAULT
VIN = 12V, VIN - VFAULT
6
7
8.3
V
Lx Start-Up Threshold
LXStart_thres
1.3
1.4
1.5
V
Lx Start-Up Current
IlxStart-up
1
3.5
5
mA
SMBus/I2C INTERFACE LOGIC LEVEL
Guaranteed Range for Data, Clock Input
VIL
Low Voltage
0.8
V
Guaranteed Range for Data, Clock Input
VIH
High Voltage
1.5
VDD
V
SMBus/I2C Output Data Line Logic Low
Voltage
VOL
IPULLUP = 4mA
0.17
V
Input Leakage On SMBData/SMBClk
ILEAK
Measured at 4.8V
-10
SMBus/I2C TIMING SPECIFICATIONS (Note 10)
Minimum Time Between EN high and
tEN-SMB/I2C 1µF capacitor on VDC
2
SMBus/I2C Enabled
10
µA
ms
Pulse Width Suppression on
SMBCLK/SMBDAT
PWS
0.15
0.45
µs
SMBus Clock Frequency
Bus Free Time Between Stop and Start
Condition
fSMB
tBUF
400
kHz
1.3
µs
Hold Time After (Repeated) START
Condition. After this Period, the First
Clock is Generated
tHD:STA
0.6
µs
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Clock Low Period
Clock High Period
Clock/Data Fall Time
tSU:STA
tSU:STO
tHD:DAT
tSU:DAT
tLOW
tHIGH
tF
0.6
µs
0.6
µs
300
ns
100
ns
1.3
µs
0.6
µs
300
ns
FN7633 Rev.3.00
Sep 19, 2017
Page 7 of 28
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