ISL97649A Просмотр технического описания (PDF) - Renesas Electronics
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ISL97649A Datasheet PDF : 22 Pages
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ISL97649A
140
VGL = -6V, SINGLE STAGE CHARGE PUMP
120
100
80
FREQ = 600kHz
FREQ = 1.2MHz
60
40
20
0
0
20
40
60
80
100
IVGL (mA)
FIGURE 15. FLYING CAPACITANCE vs VGL LOADING
700
VGH = 22V, TWO-STAGE CHARGEPUMP
600
500
400
FREQ = 600kHz
FREQ = 1.2MHz
300
200
100
0
0
20
40
60
80
100
IVGH (mA)
FIGURE 16. FLYING CAPACITANCE vs VGH LOADING
VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the back
plane of an LCD display. This plane is capacitively coupled to the
pixel drive voltage, which alternately cycles positive and negative at
the line rate for the display. Thus, the amplifier must be capable of
sourcing and sinking pulses of current, which can occasionally be
quite large (in the range of 100mA for typical applications).
The ISL97649A VCOM amplifier's output current is limited to
225mA typical. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable operation
of the part. It does not necessarily prevent a large temperature
rise if the current is maintained. (In this case, the whole chip may
be shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than this
limit, the reservoir capacitor will provide the excess and the
amplifier will top the reservoir capacitor back up once the pulse
has stopped. This will happen in the µs time scale in practical
systems and for pulses 2 or 3 times the current limit; the VCOM
voltage will have settled again before the next line is processed.
DCP Memory Description
The ISL97649A contains one non-volatile byte known as the
Initial Value Register (IVR). It is accessed by the I2C interface
operations with Address 00h. The IVR contains the value that is
loaded into the Volatile Wiper Register (WR) at power-up.
The volatile WR and the non-volatile IVR of a DCP are accessed
with the same address.
The Access Control Register (ACR) determines which word at
address 00h is accessed (IVR or WR). The volatile ACR must be
set as follows:
When the ACR is all zeroes, which is the default at power-up:
• A read operation to address 0 outputs the value of the
non-volatile IVR.
• A write operation to address 0 writes the identical values to the
WR and IVR of the DCP.
• When the ACR is 80h:
- A read operation to address 0 outputs the value of the
volatile WR.
- A write operation to address 0 only writes to the
volatile WR.
It is not possible to write to an IVR without writing the same value
to its WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be written
to address 2.
TABLE 6. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2
-
ACR
1
Reserved
0
IVR
WR
WR: Wiper Register, IVR: Initial value Register.
I2C Serial Interface
The ISL97649A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data on to the bus as
a transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the DCP of the ISL97649A operates as a slave device
in all applications. The fall and rise time of SDA and SCL signal
should be in the range listed in Table 8. Capacitive load on I2C
bus is also specified in Table 8.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 17). On
power-up of the ISL97649A, the SDA pin is in the input mode.
FN7928 Rev 3.00
June 27, 2013
Page 14 of 22
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