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LP62S16128B-I

128K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise And Fall Time

Input and Output Timing Reference Levels

Output Load

LP62S16128B-I Series

0.4V to 2.4V

5 ns

1.5V

See Figures 1 and 2

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = -40°C to 85°C)

Figure 2. Output Load for tCLZ, tOLZ, tBHZ, tBLZ,

tCHZ, tOHZ, tWHZ, and tOW

Symbol

Parameter

Min. Max. Unit

Conditions

VDR

VCC for Data Retention

2.0

3.6

V

CE ≥ VCC - 0.2V or

LB = HB ≥ VCC-0.2V

ICCDR

Data Retention Current

VCC = 2V,

-

3*

µA

CE ≥ VCC - 0.2V or

LB = HB ≥ VCC-0.2V

VIN ≥ VCC - 0.2V or VIN ≤ 0.2V

tCDR

Chip Disable to Data Retention Time

0

-

ns

tR

Operation Recovery Time

tRC

-

ns See Retention Waveform

VCC Rising Time from Data Retention

tVR

Voltage to Operating Voltage

5

-

ms

* LP62S16128B-70LLI

ICCDR: max. 1µA at TA = 0°C to + 40°C

(August, 2001, Version 1.0)

11

AMIC Technology, Inc.

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