MAX192ACAP Просмотр технического описания (PDF) - Maxim Integrated

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MAX192ACAP

Low-Power, 8-Channel,Serial 10-Bit ADC

Maxim Integrated 

Low-Power, 8-Channel,

Serial 10-Bit ADC

CS 18

SCLK 19

DIN 17

SHDN 10

CH0 1

CH1 2

CH2 3

CH3 4

CH4 5

CH5 6

CH6 7

CH7 8

AGND 13

AGND 9

REFADJ 12

VREF 11

INPUT

SHIFT

REGISTER

CONTROL

LOGIC

INT

CLOCK

ANALOG

INPUT

T/H

MUX

OUTPUT

SHIFT

REGISTER

CLOCK

IN SAR

ADC

OUT

REF

+2.46V

REFERENCE

A ≈ 1.65

20k

+4.096V

MAX192

15 DOUT

16 SSTRB

20 VDD

14 DGND

CAPACITIVE DAC

VREF

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AGND

INPUT CHOLD

MUX –

+

COMPARATOR

ZERO

16pF

CSWITCH

TRACK

10k

RS

HOLD

T/H

SWITCH

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.

DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

Figure 3. Block Diagram

Detailed Description

The MAX192 uses a successive-approximation conver-

sion technique and input track/hold (T/H) circuitry to

convert an analog signal to a 10-bit digital output. A

flexible serial interface provides easy interface to

microprocessors. No external hold capacitors are

required. Figure 3 shows the block diagram for the

MAX192.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com-

parator is illustrated in the Equivalent Input Circuit

(Figure 4). In single-ended mode, IN+ is internally

switched to CH0–CH7 and IN- is switched to AGND. In

differential mode, IN+ and IN- are selected from pairs

of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer

to Tables 1 and 2 to configure the channels.

In differential mode, IN- and IN+ are internally switched

to either one of the analog inputs. This configuration is

pseudo-differential to the effect that only the signal at

IN+ is sampled. The return side (IN-) must remain sta-

ble within ±0.5LSB (±0.1LSB for best results) with

Figure 4. Equivalent Input Circuit

respect to AGND during a conversion. Accomplish this

by connecting a 0.1µF capacitor from AIN- (the select-

ed analog input, respectively) to AGND.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor CHOLD. The

acquisition interval spans three SCLK cycles and ends

on the falling SCLK edge after the last bit of the input

control word has been entered. At the end of the acqui-

sition interval, the T/H switch opens, retaining charge

on CHOLD as a sample of the signal at IN+.

The conversion interval begins with the input multiplex-

er switching CHOLD from the positive input (IN+) to the

negative input (IN-). In single-ended mode, IN- is

simply AGND. This unbalances node ZERO at the input

of the comparator. The capacitive DAC adjusts during

the remainder of the conversion cycle to restore its

node ZERO to 0V within the limits of its resolution. This

action is equivalent to transferring a charge of

16pF x (VIN+ - VIN-) from CHOLD to the binary-weighted

capacitive DAC, which in turn forms a digital represen-

tation of the analog input signal.

_______________________________________________________________________________________ 7

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