MAX192ACAP Просмотр технического описания (PDF) - Maxim Integrated

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MAX192ACAP

Low-Power, 8-Channel,Serial 10-Bit ADC

Maxim Integrated 

Low-Power, 8-Channel,

Serial 10-Bit ADCs

PIN

1–8

9, 13

10

11

12

14

15

16

17

18

19

20

NAME

CH0–CH7

AGND

SHDN

VREF

REFADJ

DGND

DOUT

SSTRB

DIN

CS

SCLK

VDD

Pin Description

FUNCTION

Sampling Analog Inputs

Analog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to

analog ground.

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur-

rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-

er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external

compensation mode.

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.

Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an

input when used with a precision external reference.

Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to VDD.

Digital Ground

Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is

high.

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D

conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high

for one clock period before the MSB decision. SSTRB is high impedance when CS is high

(external mode).

Serial Data Input. Data is clocked in at the rising edge of SCLK.

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT

is high impedance.

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

Positive Supply Voltage, +5V ±5%

+5V

DOUT

3k

DOUT

3k

CLOAD

CLOAD

DGND

DGND

a) High-Z to VOH and VOL to VOH

b) High-Z to VOL and VOH to VOL

Figure 1. Load Circuits for Enable Time

+3V

DOUT

3k

DOUT

3k

DGND

CLOAD

CLOAD

DGND

a) VOH to High-Z

b) VOL to High-Z

Figure 2. Load Circuits for Disabled Time

6 ________________________________________________________________________________________________

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