SL23EP08 Просмотр технического описания (PDF) - Silicon Laboratories

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SL23EP08

Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)

Silicon Laboratories 

SL23EP08

Device

SL23EP08-1

SL23EP08-1H

SL23EP08-2

SL23EP08-2

SL23EP08-3

SL23EP08-3

SL23EP08-4

SL23EP08-5H

Feedback From

Bank-A Frequency

Bank-A or Bank-B

Reference

Bank-A or Bank-B

Reference

Bank-A

Reference

Bank-B

2x Reference

Bank-A

2X Reference

Bank-B

4X Reference

Bank-A or Bank-B

2X Reference

Bank-A or Bank-B

Reference /2

Table 3. Available SL23EP08 Configurations

Bank-B Frequency

Reference

Reference

Reference/2

Reference

Reference[2]

2X Reference

2X Reference

Reference /2

Notes:

1. Outputs are inverted on SL23EP08-2 and SL23EP08-3 in PLL bypass mode when S2=1 and S1=0.

2. Output phase is either 0° or 180° with respect to CLKIN input. If phase integrity is required, use the SL23EP08-2.

1500

1000

500

0

-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30

-500

-1000

-1500

Output Load Difference: FBK Load – CLKA or CLKB Load (pF)

Figure 1. CLKIN Input to CLKA and CLKB Delay

Rev 1.0, May 18, 2006

Page 4 of 15

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