CXD3511Q Просмотр технического описания (PDF) - Sony Semiconductor

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CXD3511Q

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3511Q

Description of Operation

1. Description of Input Pins

(a) System clear pins (XCLR1, XCLR2 and XCLR3)

All internal circuits are initialized by setting XCLR1 (Pin 27) low. In addition, the internal PLL is initialized by

setting XCLR2 (Pin 28) low, and RGB output is initialized (preset) by setting XCLR3 (Pin 29) low.

Initialization should be performed when power is turned on. There are no particular restrictions on the

initialization order.

(b) Sync signal input pins (HDIN and VDIN)

Horizontal and vertical separate sync signals are input to HDIN (Pin 31) and VDIN (Pin 32), respectively. The

CXD3511Q supports only non-interlace sync signals with a dot clock of 200MHz or less.

(c) Master clock input pins (CLKP/CLKN and CLKC)

Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The

master clock input pins have two systems consisting of CLKP/CLKN (Pins 38 and 39) for small-amplitude

differential input (center level: 2.0V, amplitude: ±0.4V), and CLKC (Pin 35) for CMOS level input. In addition, be

sure to make the number of dot clocks in 1H as even number.

Note that if there is an odd number of dot clocks, the internal phase compensation PLL will not operate

properly.

(d) Clock selection pins (CLKSEL1 and CLKSEL2)

The master clock input pins can input either the system dot clock or the 1/2 frequency-divided clock. The

internal clock path is selected according to CLKSEL1 (Pin 41) and CLKSEL2 (Pin 44).

Symbol

Function

CLKSEL1 Input clock selection

CLKSEL2 Clock input pin selection

L

CLKP/CLKN input

Dot clock input

Setting

H

CLKC input

1/2 frequency-divided clock input

(e) PLL setting pin (PLLDIV)

PLLDIV (Pin 45) sets the divider setting of the internal phase compensation PLL circuit. Set PLLDIV low when

the internal clock frequency is 55 to 100MHz, or high when 27.5 to 55MHz. In addition, note that the frequency

of the clock input to the CXD3511Q must be within the phase compensation PLL operating range, even during

free running.

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