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IDT7198L

CMOS STATIC RAMs 64K (16K x 4-BIT) Added Chip Select and Output Controls

Integrated Device Technology 

IDT7198S/L

CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls

TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)

tRC

ADDRESS

DATAOUT

tAA

tOH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)

CS1,2

DATAOUT

ICC

VCC SUPPLY

CURRENT ISB

tACS1, 2

tCLZ1, 2 (5)

tPU

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continuously selected, CS1 is LOW, CS2 is LOW.

3. Address valid prior to or coincident with CS1 and or CS2 transition LOW.

4. OE is LOW.

5. Transition is measured ±200mV from steady state voltage.

MILITARY TEMPERATURE RANGE

tOH

DATA VALID

2985 drw 08

tCHZ1, 2 (5)

DATA VALID

tPD

2985 drw 09

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

7198S20

7198L20

7198S25 7198S35/45 7198S55

7198L25 7198L35/45 7198L55

7198S70

7198L70

7198S85

7198L85

Symbol

Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Write Cycle

tWC

Write Cycle Time

tCW1,2(1) Chip Select to End-of-Write

17 — 20 — 30/40 — 50 — 60 — 75 — ns

17 — 20 — 25/35 — 50 — 60 — 75 — ns

tAW

Address Valid to End-of-Write

17 — 20 — 25/35 — 50 — 60 — 75 — ns

tAS

Address Set-up Time

0 — 0 — 0 — 0 — 0 — 0 — ns

tWP

Write Pulse Width

17 — 20 — 25/35 — 50 — 60 — 75 — ns

tWR1,2 Write Recovery Time

tWHZ(2) Write Enable to Output in High-Z

0 — 0 — 0 — 0 — 0 — 0 — ns

— 5/6 — 7 — 10/15 — 25 — 30 — 40 ns

tDW

Data Valid to End-of-Write

10 — 13 — 15/20 — 25 — 30 — 35 — ns

tDH

tOW(2)

Data Hold Time

Output Active from End-of-Write

0 — 0 — 0 — 0 — 0 — 0 — ns

5 — 5 — 5 — 5 — 5 — 5 — ns

NOTES:

1. Both chip selects must be active low for the device to be selected.

2. This parameter is guaranteed by device characterization but is not production tested.

2985 tbl 12

6.4

6

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