IDT7198L Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
Список матч
IDT7198L
Integrated Device Technology
IDT7198L Datasheet PDF : 8 Pages
| |||
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, Military Temperature Range)
7198S20
7198L20
7198S25 7198S35/45 7198S55
7198L25 7198L35/45 7198L55
7198S70
7198L70
7198S85
7198L85
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
20 — 25 — 35/45 — 55 — 70 — 85 — ns
tAA
Address Access Time
tACS1,2(1) Chip Select-1,2 Access Time
tCLZ1,2(2) Chip Select-1,2 to Output in Low-Z
— 19 — 25 — 35/45 — 55 — 70 — 85 ns
— 20 — 25 — 35/45 — 55 — 70 — 85 ns
5 — 5 — 5 — 5 — 5 — 5 — ns
tOE
Output Enable to Output Valid
tOLZ(2) Output Enable to Output in Low-Z
tCHZ1,2(2) Chip Select 1,2 to Output in High-Z
tOHZ(2) Output Disable to Output in High-Z
— 9 — 11 — 20/25 — 35 — 45 — 55 ns
5 — 5 — 5 — 5 — 5 — 5 — ns
— 8 — 10 — 14 — 20 — 25 — 30 ns
— 8 — 9 — 15 — 20 — 25 — 30 ns
tOH
Output Hold from Address Change
5 — 5 — 5 — 5 — 5 — 5 — ns
tPU(2) Chip Select to Power Up Time
0 — 0 — 0 — 0 — 0 — 0 — ns
tPD(2) Chip Deselect to Power Down Time — 20 — 25 — 35/45 — 55 — 70 — 85 ns
NOTES:
1. Both chip selects must be active low for the device to be selected.
2. This parameter is guaranteed by device characterization but is not production tested.
2985 tbl 11
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
tRC
tAA
OE
CS1, 2
DATAOUT
tOE
tOLZ (5)
tACS1, 2
tCLZ1, 2 (5)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is LOW.
3. Address valid prior to or coincident with CS1 and or CS2 transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state voltage.
tOH
tOHZ(5)
tCHZ1, 2 (5)
DATA VALID
2985 drw 07
6.4
5
Share Link: