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CDB5503

Non-aliasing, 16- & 20-bit A/D Converters

Cirrus Logic 

CS5501 CS5503

CS5501/CS5503

gate oscillator is designed to properly operate

without additional loading capacitors when using

a 4.096 MHz (or 4 MHz) crystal. If other crystal

frequencies or if ceramic resonators are used,

loading capacitors may be necessary for reliable

operation of the oscillator. Table 1 illustrates some

typical capacitor values to be used with selected

resonating elements.

Resonators

Ceramic

200 kHz

455 kHz

1.0 MHz

2.0 MHz

Crystals

2.000 MHz

3.579 MHz

4.096 MHz

C1

330pF

100pF

50pF

20pF

30pF

20pF

None

C2

470pF

100pF

50pF

20pF

30pF

20pF

None

Table 1. Resonator Loading Capacitors

CLKOUT (pin 2) can be used to drive one exter-

nal CMOS gate for system clock requirements. In

this case, the external gate capacitance must be

taken into account when choosing the value of

C2.

Caution: A clock signal should always be present

whenever the SLEEP is inactive (SLEEP = VD+).

If no clock is provided to the part when not in

SLEEP, the part may draw excess current and

possibly even lose its calibration data. This is be-

cause the device is built using dynamic logic.

Serial Interface Logic

The CS5501 serial data output can operate in any

one of the following three different serial interface

modes depending upon the MODE pin selection:

SSC (Synchronous Self-Clocking) mode;

MODE pin tied to VD+ (+5V).

SEC (Synchronous External Clocking) mode;

MODE pin tied to DGND.

and AC (Asynchronous Communication) mode;

CS5501 only

MODE pin tied to VD- (-5V)

The CS5503 can only operate in the first two

modes, SEC and SSC.

Synchronous Self-Clocking Mode

When operated in the SSC mode (MODE pin tied

to VD+), the CS5501/CS5503 furnish both serial

output data (SDATA) and an internally-generated

serial clock (SCLK). Internal timing for the SSC

mode is illustrated in Figure 4. Figure 5 shows

detailed SSC mode timing for both the

CS5501/CS5503. A filter cycle occurs every 1024

cycles of CLKIN. During each filter cycle, the

status of CS is polled at eight specific times dur-

ing the cycle. If CS is low when it is polled, the

CS5501/CS5503 begin clocking the data bits out,

MSB first, at a SCLK output rate of CLKIN/4.

Once transmission is complete, DRDY rises and

both SDATA and SCLK outputs go into a high

impedance state. A filter cycle begins each time

DRDY falls. If the CS line is not active, DRDY

will return high 1020 clock cycles after it falls.

Four clock cycles later DRDY will fall to signal

that the serial port has been updated with new

data and that a new filter cycle has begun. The

first CS polling during a filter cycle occurs 76

clock cycles after DRDY falls (the rising edge of

CLKIN on which DRDY falls is considered clock

cycle number one). Subsequent pollings of CS oc-

cur at intervals of 128 clock cycles thereafter (76,

204, 332, etc.). The CS signal is polled at the be-

ginning of each of eight data output windows

which occur in a filter cycle. To transmit data dur-

ing any one of the eight output windows, CS must

be low at least three CLKIN cycles before it is

polled. If CS does not meet this set-up time, data

will not be transmitted during the window time.

Furthermore, CS is not latched internally and

therefore must be held low during the entire data

transmission to obtain all of the data bits.

DS31F54

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