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CDB5503

Non-aliasing, 16- & 20-bit A/D Converters

Cirrus Logic 

CS5501 CS5503

CS5501/CS5503

GENERAL DESCRIPTION

The CS5501/CS5503 are monolithic CMOS A/D

converters designed specifically for high resolu-

tion measurement of low-frequency signals. Each

device consists of a charge-balance converter (16-

Bit for the CS5501, 20-Bit for the CS5503),

calibration microcontroller with on-chip SRAM,

and serial communications port.

The CS5501/CS5503 A/D converters perform

conversions continuously and update their output

ports after every conversion (unless the serial port

is active). Conversions are performed and the se-

rial port is updated independent of external

control. Both devices are capable of measuring

either unipolar or bipolar input signals, and cali-

bration cycles may be initiated at any time to

ensure measurement accuracy.

The CS5501/CS5503 perform conversions at a

rate determined by the master clock signal. The

master clock can be set by an external clock or

with a crystal connected to the pins of the on-chip

gate oscillator. The master clock frequency deter-

mines:

1. The sample rate of the analog input signal.

2. The corner frequency of the on-chip digital

filter.

3. The output update rate of the serial output port.

The CS5501/CS5503 design includes several self-

calibration modes and several serial port interface

modes to offer users maximum system design

flexiblity.

The Delta-Sigma Conversion Method

The CS5501/CS5503 A/D converters use charge-

balance techniques to achieve low cost, high

resolution measurements. A charge-balance A/D

converter consists of two basic blocks: an analog

modulator and a digital filter. An elementary ex-

ample of a charge-balance A/D converter is a

conventional voltage-to-frequency converter and

counter. The VFC’s 1-bit output conveys infor-

DS31F54

mation in the form of frequency (or duty cycle),

which is then filtered (averaged) by the counter

for higher resolution.

S/H Amp

LP Filter

1-bit

Digital Filter

Comparator

DAC

16-bits

Figure 1. Charge Balance (Delta-Sigma) A/D Converter

The analog modulator of the CS5501/CS5503 is a

multi-order delta-sigma modulator. The modulator

consists of a 1-bit A/D converter (that is, a com-

parator) embedded in an analog feedback loop

with high open loop gain (see Figure 1). The

modulator samples and converts the input at a rate

well above the bandwidth of interest. The 1-bit

output of the comparator is sampled at intervals

based on the clock rate of the part and this infor-

mation (either a 1 or 0) is conveyed to the digital

filter. The digital filter is much more sophisticated

than a simple counter. The filter on the chip has a

6-pole low pass Gaussian response which rolls off

at 120 dB/decade (36 dB/octave). The corner fre-

quency of the digital filter scales with the master

clock frequency. In comparison, VFC’s and dual

slope converters offer (sin x)/x filtering for high

frequency rejection (see Figure 2 for a compari-

son of the characteristics of these two filter types).

When operating from a 1 MHz master clock the

digital filter in the CS5501/CS5503 offers better

than 120 dB rejection of 50 and 60 Hz line fre-

quencies and does not require any type of line

synchronization to achieve this rejection. It should

be noted that the CS5501/CS5503 will update its

output port almost at 1000 times per second when

operating from the 1 MHz clock. This is a much

higher update rate (typically by a factor of at least

50 times) than either VFCs or dual-slope convert-

ers can offer.

For a more detailed discussion on the delta-sigma

modulator see the Application note "Delta-Sigma

11

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