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HMP8112A

NTSC/PAL Video Decoder

Harris Semiconductor 

HMP8112A

7

TEMPERATURE = 25oC

6 VCC = 5V

5

4

The input sample rate converter will interpolate between

existing CLK samples to create the chroma locked (4xfSC)

samples needed for the color decoder. An interpolation is

done to create the 4xfSC pixel and a correction factor is then

applied.

INCOMING VIDEO SAMPLES

3

2

TIME

1

0

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4

GAIN CONTROL VOLTAGE

RESAMPLED VIDEO

FIGURE 3. CHROMINANCE AMPLIFIER GAIN

TIME

Reset

The RESET pin is used to return the decoder to an

initialization state. This pin should be used after a power-up

to set the part into a known state. The internal registers are

returned to their RESET state and the Serial I2C port is

returned to inactive state. The RESET pin is an active low

signal and should be asserted for minimum of 1 CLK cycle.

After a RESET or a software reset has occurred all output

pins are three-stated. The VSYNC, HSYNC, DVLD, ACTIVE

and FIELD output pins must be pulled high to ensure proper

operation. A 10K or smaller pullup resistor to VCC is

recommended.

NTSC/PAL Decoder

The NTSC/PAL decoder is designed to convert incoming

Composite or Separated (SVHS, Y/C) video into it’s YCbCr

component parts. The digital phase locked loops are

designed to synchronize to the various NTSC/PAL stan-

dards. They provide a stable internal 4xfSC (Frequency of

the Color Sub-Carrier) video clock for color demodulation,

and a line locked clock for vertical spatial pixel alignment.

The decoder uses the CLK to run the A/D converters and the

phase locked loops. This asynchronous master clock for the

decoder eliminates the need for a unique clock source in a

Multimedia application. CLK can run from 20MHz to 30MHz

when using the 16-bit Synchronous Data output Mode. The

user must program the CLK to Color Sub-Carrier Ratio to

match the CLK frequency used (see Internal Phase Locked

Loops discussion). When using the 8-bit Burst Data Output

Mode the CLK should be a 24.54MHz, 27MHz or 29.5MHz

depending on the output video standard chosen. The crystal

oscillator must have a ±50ppm accuracy and a 60/40% duty

cycle symmetry to ensure proper operation. Since the video

data from the external A/D’s are sampled at the CLK fre-

quency a sample rate converter is employed to convert the

data from the CLK rate to the internal decoding frequency of

4xfSC.

4xfSC

FIGURE 4. SAMPLE RATE CONVERSION

The decoder can be used with the following video sources:

Analog Composite - NTSC M, - PAL B, D, G, H, I, N

And Special Combination PAL N

Analog S - VHS (Y/C) - NTSC M, PAL B, D, G, H, I, N

And Special Combination PAL N

Color Separation, and Demodulation

To separate the chrominance modulated color information

from the baseband luminance signal, a 2-Line comb filter is

employed. In NTSC signals the color information changes

phase 180o from one line to the next. This interleaves the

chrominance information at half line intervals throughout the

NTSC video spectrum. Therefore, NTSC has 227.5 cycles of

chrominance per NTSC line. The half of a cycle causes the

next reference burst to be 180o out of phase with the previ-

ous line’s burst. The 2-Line comb efficiently removes the

chrominance information from the baseband luminance sig-

nal. When decoding NTSC, the decoder maintains full lumi-

nance bandwidth horizontally throughout the chrominance

carrier frequency range. Unlike most 2 line comb filter sepa-

ration techniques, vertical bandwidth is maintained by

means of a proprietary transform technique.

Reset

The RESET pin is used to return the decoder to an initializa-

tion state. This pin should be used after a power-up to set the

part into a known state. The internal registers are returned to

their RESET state and the Serial I2C port is returned to inac-

tive state. The RESET pin is an active low signal and should

be asserted for minimum of 1 CLK cycle. After a RESET or a

software reset has occurred all output pins are three-stated.

The VSYNC, HSYNC, DVLD, ACTIVE and FIELD output pins

must be pulled high to ensure proper operation. A 10K or

smaller pullup resistor to VCC is recommended.

4-6

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