HMP8112A Просмотр технического описания (PDF) - Harris Semiconductor
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HMP8112A Datasheet PDF : 40 Pages
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HMP8112A
I 2C Control Interface
The HMP8112A utilizes an I2C control bus interface to pro-
gram the internal configuration registers. This standard
mode (up to 100 KBPS) interface consists of the bidirectional
Serial Data Line (SDA) and the Serial Clock Line (SCL). The
implementation on the HMP8112A is a simple slave interface
that will not respond to general calls and cannot initiate a
transfer. The SDA and SCL control pins should be pulled
high through external 4kΩ pullup resistors to VCC.
The I2C clock/data timing is shown below in Figure 16. The
HMP8112A always uses chip address 0x88. There are 28
internal registers used to program and configure the
decoder. The I2C control port contains a pointer register that
auto-increments through the entire register space and can
be written. The autoincrement pointer will wrap after the last
register has been accessed (Product ID Register) and
should be set to the desired starting address each time an
access is started. For a write transfer, the I2C device base
address is the first part of a serial transfer. Then the internal
register pointer is loaded and a series of registers can be
written. If multiple registers are written, the pointer register
will autoincrement up through the register address space. A
stop cycle is used to end the transfer after the desired num-
ber of registers are programmed.
For a read transfer, the I2C device address is the first part of
the serial transfer. Then the internal register pointer is
loaded. At this point another start cycle is initiated to access
the individual registers. Figure 18 shows the programming
flow for read transfer of the internal registers. Multiple regis-
ters can be read and the pointer register will autoincrement
up through the pointer register address space. On the last
data read, an acknowledge should not be issued. A stop
cycle is used to end the transfer after the desired number of
registers are read.
The HMP8112A contains a product ID register that can be
used to identify the presence of a board during a Plug ’n Play
detection software algorithm. The Product ID Code register is
at sub address 0x1B and always returns a data value of 0x12.
tBUF
tSU:DATA
SDA
tHD:DATA
SCL
tLOW tHIGH
tR tF
FIGURE 16. I2C TIMING DIAGRAM
tSU:STOP
SDA
SCL
S
1-7
8
9
1-7
8
START
CONDITION
ADDRESS
R/W
ACK
DATA
FIGURE 17. I2C SERIAL DATA FLOW
9
ACK
P
STOP
CONDITION
DATA WRITE
1000 1000
S CHIP ADDR A
0x88
DATA READ
1000 1000 (R/W)
S CHIP ADDR A
0x88
SUB ADDR
SUB ADDR
A DATA A DATA A P
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
FROM MASTER
FROM HMP8112A
AS
CHIP ADDR
0x89
A DATA
A DATA
NA P
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
FIGURE 18. REGISTER WRITE/READ FLOW
4-13
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