HMP8112A Просмотр технического описания (PDF) - Harris Semiconductor

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HMP8112A

NTSC/PAL Video Decoder

Harris Semiconductor 

HMP8112A

CLK

DVLD

NOTE 3

ACTIVE

NOTE 2

Y[7-0]

YN

Y0

Y1

Y2

Y3

Y4

NOTE 1

CbCr[7-0]

CrN

Cb0

Cr0

Cb2

Cr2

Cb4

tDVLD

NOTES:

1. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle

due to the 4:2:2 subsampling. YN the last valid pixel in the blanking period.

2. ACTIVE is asserted per Figure 13.

3. DVLD is asserted for every valid pixel during both active and blanking regions. DVLD is not a 50% duty cycle synchronous output and will

appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.

FIGURE 14. OUTPUT TIMING 16-BIT MODE

CLK

DVLD

NOTE 6

ACTIVE

NOTE 5

Y[7-0]

Cb0

Y0

Cr0

Y1

Cb2

Y2

Cr2

Y3

Cb4

tDVLD

NOTE 4

NOTES:

4. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle

due to the 4:2:2 subsampling. Pixel data is not output during the blanking period.

5. ACTIVE stays asserted as soon as 8-Bit mode is selected.

6. DVLD is asserted for every valid pixel during the active region only per Figure 13. DVLD may deassert briefly during the active video region

as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.

FIGURE 15. OUTPUT TIMING 8-BIT MODE

4-12

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