HI20206 Просмотр технического описания (PDF) - Intersil
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HI20206 Datasheet PDF : 13 Pages
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HI20206
Electrical Specifications TA = 25oC, AVCC = DVCC = 5V, AGND = DGND = 0V (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
Glitch Energy
GE
VSET - AGND = 0.8V,
-
160
RL>10kΩ, fCLK = 1MHz,
Digital Ramp Output,
See Figure 6 (Note 5)
Rise Time (Note 6)
Fall Time (Note 6)
Settling Time
NOTES:
tr
tf
tSET
VSET - AGND = 0.8V
See Figure 4
-
5.5
-
5.0
-
16
3. AVCC - VO.
4. Maximum value among
100 × V-V----OO----FF----SS----((--GR----)) – 1 , 100 × -VV----OO----F-F---SS----((--GB----)) – 1 , or 100 × V-V----OO----FF----SS----((--RB----)) – 1 .
5. Observe the glitch which is generated when the digital input varies as follows:
0 0 1 1 1 1 1 1 —0 1 0 0 0 0 0 0
01 1 1 1 1 1 1 1 — 1 0 0 0 0 0 0 0
10 1 1 1 1 1 1 1 — 1 1 0 0 0 0 0 0
6. The time required for the D/A OUT to arrive at 90% of its final value from 10%.
INPUT CORRESPONDING TABLE
INPUT CODE
OUTPUT VOLTAGE
MSB
LSB
11111111
•
VCC + VOFFSET
•
•
10000000
•
VCC + VOFFSET -0.5V
•
•
•
•
•
00000000
VCC + VOFFSET -1.0V
NOTE: In case the output voltage full scale is 1V (1 LSB = 3.92mV).
Test Circuits
MAX
-
UNITS
pV/s
-
ns
-
ns
-
ns
DVCC
D1 ~ D8
37
39 - 42
1~4
D1
8 (R)
ROUT
D2
D1 ~ D8
5 ~ 12
35
GOUT
33
8 (G)
BOUT
31
V
D8
D1 ~ D8
8 (B)
13 ~ 20
29 AVCC
VREF
27
VSET
DGND
26 +
3K
-V
25
33µF
CLK TTL LEVEL
21
CLK
22
HI20206
FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUITS
10-6
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