HI20206 Просмотр технического описания (PDF) - Intersil

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HI20206

Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter

Intersil 

Timing Diagram

t1

t12

t2

tPW1 tPW0

HI20206

t3

t34

t4

CLK

tX

tY

DATA

tH

tS

tH

tS

100%

90%

D/A OUT

10%

0%

VTH = 1.5V

0%

10%

VTH = 1.4V

VTH: THRESHOLD LEVEL

90%

100%

tr

tf

NOTE: At the time t = tX, the data of individual bits are switched and

thereafter, when the CLK becomes L → H at t = t2, the D/A OUT is

varied synchronous with it. That is, the D/A OUT is synchronous with

NOTE: At the time t = tY, the data of individual bits are switched and

thereafter when the CLK becomes L → H at t = t4, the D/A OUT is

varied synchronous with it. That is, the D/A OUT is synchronous with

the rise of the CLK. [In this case, fetching of the data is carried out at the rise of the CLK. [In this case, fetching of the data is carried out at

the fall of the CLK (at the time when t = t12)].

the fall of the CLK (at the time when t = t4)].

FIGURE 8. TIMING CHART

Notes On Use

(1) Setting of pin 26 (VSET)

The full scale of the D/A output voltage changes by apply-

ing voltage to pin 26 (VSET). When load is connected to

pin 27 (VREF), DC voltage of 1.2V is issued and the said

voltage is dropped to 0.8V by resistance division.

When the 0.8V is applied to pin 26 (VSET), the D/A

output of 1VP-P can be obtained.

(Example of use):

See R vs IREF of Figure 14. The calculation

expression is as follows:

R = VREF/IREF.

2. Adjust the volume so that the RGB output voltage

full scale becomes 1V.

(At this point, it becomes R1: R2 = 1:2).

5.0

27 VREF

R1

26 VSET

R

R2

25

AGND

FIGURE 9.

(Adjustment Method)

1. The resistance R is determined in accordance with

the recommended operating condition of IREF,

(current flowing through resistance R).

1.0

0.3

0.1

0.1

0.2

1

5

PIN CURRENT IREF (mA)

FIGURE 10. RESISTANCE vs VREF PIN CURRENT

10-10

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