CY7C1041CV33-15ZXI(2008) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1041CV33-15ZXI
(Rev.:2008)

4-Mbit (256K x 16) Static RAM

Cypress Semiconductor 

CY7C1041CV33

Switching Waveforms

Figure 4. Read Cycle No. 1 (Address Transition Controlled)[10, 11]

tRRCC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

Figure 5. Read Cycle No. 2 (OE Controlled)[11, 12]

ADDRESS

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

tHZOE

DATA VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Notes

10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.

11. WE is HIGH for read cycle.

12. Address valid prior to or coincident with CE transition LOW.

Document Number: 38-05134 Rev. *I

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