HEF4794B-Q100 Просмотр технического описания (PDF) - NXP Semiconductors.
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HEF4794B-Q100 Datasheet PDF : 14 Pages
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Nexperia
HEF4794B-Q100
8-stage shift-and-store register LED driver
Symbol Parameter
tsu
set-up time
th
hold time
fclk(max) maximum clock
frequency
Conditions
VDD
D to CP; see Fig. 9 5 V
10 V
15 V
D to CP; see Fig. 9 5 V
10 V
15 V
CP; see Fig. 6
5V
10 V
15 V
Extrapolation formula
Min Typ Max Unit
60 30
- ns
20 10
- ns
15
5
- ns
+5 -15
- ns
20
5
- ns
20
5
- ns
5
10
- MHz
11 22
- MHz
14 28
- MHz
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] ten is the same as tPZL and tdis is the same as tPLZ
[3] tt is the same as tTLH and tTHL
Table 8. Dynamic power dissipation
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter
VDD
PD
dynamic power dissipation 5 V
10 V
15 V
Typical formula
PD = 1 200 x fi + Σ(fo x CL) x VDD2 μW
PD = 5 550 x fi + Σ(fo x CL) x VDD2 μW
PD = 15 000 x fi + Σ(fo x CL) x VDD2 μW
Where
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
Σ(fo × CL) = sum of the outputs;
VDD = supply voltage in V.
10.1. Waveforms and test circuit
VI
CP input
VSS
VDD
QPn output
VOL
1/fclk(max)
VM
tW
tW
tPLZ
VX
tPLH
tPZL
VY
tPHL
Fig. 6.
VOH
90 %
QS1 output
VM
VOL
VOH
10 %
tTLH
90 %
tPLH
tTHL
tPHL
QS2 output
VM
VOL
10 %
tTLH
tTHL
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Parallel output measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Propagation delay clock (CP) to output (QPn, QS1, QS2), clock pulse width and maximum clock frequency
HEF4794B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 November 2018
© Nexperia B.V. 2018. All rights reserved
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