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RV5C386A_03

I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION

RICOH Co.,Ltd. 

RV5C386A

2.2-4 XSTP

Oscillation Halt Sensing Bit

XSTP

0

1

Description

Sensing a normal condition of oscillation

Sensing a halt of oscillation

(Default setting)

The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator.

· The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as

power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the restart of

oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data after power-on or

a drop in supply voltage.

· When the XSTP bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1,

and control register 2, stopping the output from the INTRA and INTRB pins.

· The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely, setting

the XSTP bit to 1 causes no event.

2.2-5 SCRATCH2

Scratch Bit 2

SCRATCH2

0

1

Description

(Default setting)

The SCRATCH2 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH2 bit

will be set to 0 when the XSTP bit is set to 1 in the control register 2.

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