74ABT544(2009) Просмотр технического описания (PDF) - NXP Semiconductors.
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74ABT544
(Rev.:2009)
(Rev.:2009)
NXP Semiconductors.
74ABT544 Datasheet PDF : 15 Pages
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NXP Semiconductors
74ABT544
Octal latched transceiver with dual enable; inverting; 3-state
3.0 V
An, Bn
GND
3.0 V
LEAB, LEBA,
EAB, EBA
GND
VM
VM
tsu(H) th(H)
VM
VM
VM
tsu(L)
tWL
th(L)
VM
001aae905
Fig 9.
VM = 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Data set-up and hold times and latch enable pulse width
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
tr
VI
positive
pulse
90 %
VM
10 %
0V
tW
90 %
VM
tr
tf
VM
10 %
001aac221
VI
G
VCC
VO
DUT
RT
a. Input pulse definition
b. Test circuit
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 10. Load circuitry for switching times
VEXT
RL
CL
RL
mna616
Table 8.
Input
VI
3.0 V
Test data
fI
1 MHz
tW
500 ns
tr, tf
≤ 2.5 ns
Load
CL
50 pF
RL
500 Ω
VEXT
tPHL, tPLH
open
tPZH, tPHZ
open
tPZL, tPLZ
7.0 V
74ABT544_4
Product data sheet
Rev. 04 — 15 January 2009
© NXP B.V. 2010. All rights reserved.
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