HEF40098B Просмотр технического описания (PDF) - NXP Semiconductors.
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HEF40098B Datasheet PDF : 12 Pages
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NXP Semiconductors
HEF40098B
3-state hex inverting buffer
11. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 6; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Extrapolation formula[1] Min Typ Max Unit
tPHL
HIGH to LOW
nAn to nYn;
5V
70 ns + (0.20 ns/pF) CL -
propagation delay see Figure 4
10 V
31 ns + (0.08 ns/pF) CL -
80
160 ns
35
70 ns
15 V
22 ns + (0.06 ns/pF) CL -
25
50 ns
tPLH
LOW to HIGH
nAn to nYn;
5V
50 ns + (0.30 ns/pF) CL -
propagation delay see Figure 4
10 V
24 ns + (0.13 ns/pF) CL -
65
130 ns
30
60 ns
15 V
23 ns + (0.05 ns/pF) CL -
25
50 ns
tTHL
HIGH to LOW output see Figure 4
5V
15 ns + (0.30 ns/pF) CL -
transition time
10 V
10 ns + (0.11 ns/pF) CL -
30
60 ns
15
30 ns
15 V
7 ns + (0.07 ns/pF) CL -
10
20 ns
tTLH
LOW to HIGH output see Figure 4
5V
10 ns + (0.50 ns/pF) CL -
transition time
10 V
8 ns + (0.24 ns/pF) CL -
35
70 ns
20
40 ns
15 V
6 ns + (0.18 ns/pF) CL -
15
30 ns
tPHZ
HiGH to OFF-state nOE, to nYn;
5V
propagation delay see Figure 5
10 V
-
45
85 ns
-
35
65 ns
15 V
-
30
60 ns
tPLZ
LOW to OFF-state nOE, to nYn;
5V
propagation delay see Figure 5
10 V
-
65
135 ns
-
40
80 ns
15 V
-
35
70 ns
tPZH
OFF-state to HIGH nOE, to nYn;
5V
propagation delay see Figure 5
10 V
-
70
140 ns
-
35
75 ns
15 V
-
30
65 ns
tPZL
OFF-state to LOW nOE, to nYn;
5V
propagation delay see Figure 5
10 V
-
90
185 ns
-
40
85 ns
15 V
-
35
70 ns
[1] The typical value of the propagation delay and transition times are calculated from the extrapolation formula as shown (CL in pF).
Table 8. Dynamic power dissipation PD
PD can be calculated (in µW) from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter
VDD
Typical formula for PD (µW)
where:
PD
dynamic power 5 V
PD = 5000 × fi + Σ(fo × CL) × VDD2
fi = input frequency in MHz,
dissipation
10 V
PD = 22800 × fi + Σ(fo × CL) × VDD2
fo = output frequency in MHz,
15 V
PD = 81000 × fi + Σ(fo × CL) × VDD2
CL = output load capacitance in pF,
VDD = supply voltage in V,
Σ(CL × fo) = sum of the outputs.
HEF40098B_5
Product data sheet
Rev. 05 — 31 October 2008
© NXP B.V. 2008. All rights reserved.
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