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FEDL7029-04
ML7029
TIMING DIAGRAM
Transmit Side PCM/ADPCM Data Interface
BCLK
SYNC
PCMSO
tBS
tBS
tWS
tXD1
tXD2
MSB
tSDX
IS
tSDX MSB
tXD3
LSB
tXD3
LSB
Receive Side PCM/ADPCM Data Interface
BCLK
tBS
tBS
tWS
SYNC
tRD1
tRD2
PCMRO
IR
MSB
tSDR
tDS
tDH
MSB
tRD3
LSB
tRD3
LSB
Figure 3-1 PCM/ADPCM Data Interface (Continuous BCLK)
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