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ISP1583

Hi-Speed USB peripheral controller

NXP Semiconductors. 

NXP Semiconductors

ISP1583

Hi-Speed USB peripheral controller

Table 4. Endpoint access and programmability

Endpoint

identifier

Maximum packet Double buffering Endpoint type

size

EP0SETUP 8 bytes (fixed)

no

set-up token

EP0RX

64 bytes (fixed)

no

control OUT

EP0TX

64 bytes (fixed)

no

control IN

EP1RX

programmable

yes

programmable

EP1TX

programmable

yes

programmable

EP2RX

programmable

yes

programmable

EP2TX

programmable

yes

programmable

EP3RX

programmable

yes

programmable

EP3TX

programmable

yes

programmable

EP4RX

programmable

yes

programmable

EP4TX

programmable

yes

programmable

EP5RX

programmable

yes

programmable

EP5TX

programmable

yes

programmable

EP6RX

programmable

yes

programmable

EP6TX

programmable

yes

programmable

EP7RX

programmable

yes

programmable

EP7TX

programmable

yes

programmable

Direction

OUT

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

The ISP1583 operates on a 12 MHz crystal oscillator. An integrated 40 × PLL clock

multiplier generates the internal sampling clock of 480 MHz.

8.1 DMA interface, DMA handler and DMA registers

The DMA block can be subdivided into two blocks: DMA handler and DMA interface.

The firmware writes to the DMA Command register to start a DMA transfer (see Table 51).

The command opcode determines whether a generic DMA, Parallel I/O (PIO) or

Multi-word DMA (MDMA) transfer will start. The handler interfaces to the same FIFO

(internal RAM) as used by the USB core. On receiving the DMA command, the DMA

handler directs the data from the endpoint FIFO to the external DMA device or from the

external DMA device to the endpoint FIFO.

The DMA interface configures the timing and the DMA handshake. Data can be

transferred using either the DIOR and DIOW strobes or the DACK and DREQ

handshakes. DMA configurations are set up by writing to the DMA Configuration register

(see Table 56 and Table 57).

For an IDE-based storage interface, applicable DMA modes are PIO and MDMA

(Multi-word DMA; ATA).

For a generic DMA interface, DMA modes that can be used are Generic DMA (GDMA)

slave.

Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.

For details on DMA registers, see Section 9.4.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

© NXP B.V. 2008. All rights reserved.

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